The invention relates generally to frequency synthesizers and more particularly to a phase lock loop which, upon a change in a reference frequency, settles very quickly to a steady state condition while having a relatively narrow final loop bandwidth.
In the field of frequency synthesis, phase lock loops are employed to act as wide frequency range tracking filters and as wide frequency range frequency translators. When thus used, the phase lock loop is designed to lock a synthesized signal of a first oscillator at a first frequency and at a first phase to the phase of an incoming reference signal at another frequency. Once the frequency of the synthesized signal developed in the phase lock loop is matched to that of the incoming reference signal, steady state is said to exist. However, when the frequencies of the incoming reference signals vary from the synthesized signal, the phase lock loop experiences a transient state before the loop locks on and settles to the new incoming reference frequency. For many applications, it is important to reduce the time spent in this transient state so that this situation continues to be a problem with phase lock loop frequency synthesizers.
Generally, the loop is a modified servo system which includes a transducer mixer for receiving the reference signal and an output signal from the voltage-controlled oscillator of the phase lock loop. The transducer mixer produces an error signal which is fed to a high gain amplifier which incorporates negative feedback. As the error signal increases, a control voltage produced by the amplifier is adjusted to reduce the error signal. In the limit, the amplifier gain is very large and the error signal is driven to zero in an ideal servo system.
The output signal of the phase lock loop is a synthesized frequency which in effect is a new frequency that is developed from a combination of the reference frequencies and the frequencies developed within the phase lock loop. If the intent is to create a relatively high frequency, such as 750 MHz by way of example only, then the phase lock loop must be able to produce high frequencies but yet maintain the stability of the original source device. The source device may be a reference oscillator, such as a frequency-controlled crystal oscillator.
A frequency signal voltage v(t) is described mathematically by the following expression. EQU v(t)=A Sin (2.pi.ft+.phi.) (1)
The term (A) is defined as the amplitude of the signal voltage while the term (f) is defined as the frequency of the signal voltage. The additional term (.phi.) is defined as the phase angle of the signal voltage v(t). In the past, phase lock loop frequency synthesizers generated a synthesized frequency signal voltage. The frequency of the signal voltage was (f.sub.0) and the phase angle was designated (.phi..sub.0). The signal voltage was generated from reference signals having frequencies (f.sub.1, f.sub.2, . . . , f.sub.n) and having corresponding phase angles (.phi..sub.1, .phi..sub.2, . . . , .phi..sub.n). Thus, the frequency of the syntehsized signal voltage may be defined as
f.sub.0 =R.sub.1 f.sub.1 +R.sub.2 f.sub.2 +. . . +R.sub.n f.sub.n ( 2)
and the phase angle of the synthesized signal voltage may be defined as EQU 0=R.sub.1 .phi..sub.1 +R.sub.2 .phi..sub.2 +. . . +R.sub.n .phi..sub.n ( 3)
where the terms (R.sub.1, R.sub.2, . . . , R.sub.n) are adjustable numbers.
Generally, a typical phase lock loop frequency synthesizer of the past includes a pair of the reference frequencies f.sub.1, f.sub.2 employed to generate the synthesized output frequency f.sub.0 of the phase lock loop. The synthesizer typically would include a voltage controlled oscillator which provided the synthesized output frequency f.sub.0. The output frequency f.sub.0 is controlled by a voltage v.sub.o supplied to the oscillator and it is the voltage v.sub.o that causes the oscillator to provide the synthesized output frequency f.sub.0. A frequency transducer mixer receives the reference frequency f.sub.2 from a local oscillator and also receives the output frequency f.sub.0 from the voltage controlled oscillator. The sum and difference of the two frequencies are delivered to a low pass filter that permits only the signal represented by the difference in frequencies to pass. Thus, the frequency (f.sub.0 -f.sub.2) is received by a programmable frequency divider and divided by a number (N) providing a signal having the frequency (f.sub.0 -f.sub.2)/N.
A phase detector is provided for receiving the signal having the frequency (f.sub.0 -f.sub.2)/N from the divider and the reference frequency f .sub.1 from another local oscillator. The phase detector provides an output signal error voltage (v.sub.e) which is proportional divider having frequency (f.sub.0 -f.sub.2)/N and the reference signal having frequency f.sub.1. The output signal error voltage v.sub.e is then delivered to a loop filter which is comprised of an amplifier, a pair of resistors and a capacitor. The first resistor is an input resistor to the amplifier while the second resistor and the capacitor form a series feedback loop between the input and output of the amplifier. The loop filter operates upon the error voltage v.sub.e for providing the voltage v.sub.o which is the voltage controlled oscillator control voltage.
In operation, the typical phase lock loop frequency synthesizer of the past acts as a negative feedback servo loop which, in the steady state, drives the error voltage v.sub.e to zero by controlling the voltage controlled oscillator frequency. For the error voltage v.sub.e to be equivalent to zero, both the phases and frequencies of the signal (f.sub.0 -f.sub.2)/N and the reference signal f.sub.1 transmitted to the phase detector must be equal. When these two signals are equivalent in phase angle and frequency, the frequency of the synthesized signal voltage provided by the voltage controlled oscillator becomes EQU f.sub.0 =Nf.sub.1 +f.sub.2 ( 4)
and the phase angle of the voltage controlled oscillator becomes EQU .phi..sub.0 =N.phi..sub.1 +.phi..sub.2. (5)
Note that although the divide-by-N circuit is employed in the phase lock loop, a multiply-by-N circuit results. This is a significant feature since generally phase lock loop frequency synthesizers invert the operations performed on the voltage controlled oscillator frequency f.sub.0.
Another useful function of the phase lock loop of the prior art is that of narrowing the bandwidth. If the phase of the incoming reference signal is varied, the phase lock loop will track the phase variation only inside the loop bandwidth and thus the properties of the voltage-controlled oscillator must be relied upon. Additionally, if the phase of the reference signal is stable but includes electrical noise riding thereon, the phase lock loop will track the reference signal inside the loop bandwidth and will clip extraneous noise extending beyond the bandwidth. Thus, the result is that the phase lock loop eliminates some of the electrical noise and transient spurs outside the loop bandwidth. This characteristic is useful in a synthesizer incorporated within a communications network so that a reference frequency may be broadcast providing a transmitter signal which is essentially free of electrical noise. Thus, the loop acts as a tracking filter following the reference frequency even if the reference frequency changes.
When the reference frequency changes, the synthesized frequency developed by the voltage-controlled oscillator must also change to correspond to the change in the reference frequency. This change results in a settling time within the phase lock loop to permit the circuit to reach the steady state condition. Thus, a basic problem with the phase lock loops of the prior art is that although the bandwidth of the phase lock loop is narrower which permits eliminating electrical noise from the synthesized signal, the loop takes longer to settle to the final steady state value. The challenge is to design a phase lock loop synthesizer which includes the property of a short settling time given a narrow loop bandwidth. This relationship is clearly depicted by Equation (6) which illustrates that the settling time is proportional to the reciprocal of the bandwidth. EQU .tau..alpha.1/Bw (6)
It can be seen from this relationship that the narrower the bandwidth, then the larger the fraction 1/Bw becomes, resulting in a longer settling time in seconds. Thus, when a change occurs in the reference frequency, the time it takes for the phase lock loop to settle out and stablize into the steady state mode is controlled in part by the bandwidth.
The challenge to those skilled in the art has been to build a synthesizer that is capable of a fast settling time once the reference frequency has been changed while simultaneously having a narrow bandwidth. An example of a system which could effectively employ a phase lock loop with such characteristics is a frequency hopping system which is employed to change the frequency for encoding transmission having a fast settling time and a narrow bandwidth. Such a circuit is useful in communications system which utilize frequency hopping.
In an effort to reduce the loop settling time, phase lock loops in frequency synthesizers have previously comprised precharge and pretune circuits, very complex multiple loop configurations, and ping-pong synthesizers. The settling time reduction available from pretune and precharge circuits is limited by the accuracy resolutions of a digital-to-analog converter used in these circuits and by the uncertainty in knowing the proper control voltage of the voltage-controlled oscillator. There have been fast settling loops in the prior art, but these fast settling loops have consisted of very complex circuits with substantially higher manufacturing costs, weights, and power consumptions. Ping-pong synthesizers achieve fast settling times by switching between two relatively slow phase lock loop synthesizers.
The phase lock loop of the prior art included the amplifier which incorporated the negative feedback network having the capacitor connected therein. The time necessary to charge and discharge the capacitor was the principle limitation on the settling time for the loop. Also, the charging rate of the capacitor in normal loop operations was directly proportional to the loop bandwidth. The pretuned circuit was designed to reduce the required change in capacitor voltage.
If the voltage output of the voltage-controlled amplifier was made the sum of the amplifier voltage and a pretuned digital-to-analog converter voltage, the approximate value of the oscillator output voltage at the new reference frequency could be loaded into the digital-to-analog converter when the synthesizer frequency was changed. Under these conditions, the capacitor only had to be charged an amount to account for the uncertainty in knowing the true value of the oscillator output voltage. The settling time was reduced, but the reduction depended upon the accuracy and resolution of the digital-to-analog converter and the uncertainty in knowing the tuning curve of the voltage-controlled oscillator.
Another method included precharging the feedback capacitor to a value approximating its new value. A precharge circuit was temporarily connected to the feedback capacitor to charge it quickly when the reference frequency was changed. The reduction in the settling time again depended on how close the voltage across the feedback capacitor was brought to the required value.
If the precharge circuit was perfect, the settling time could be reduced to the point where the feedback capacitor could be charged instantly. However, the charge required on the feedback capacitor to settle the loop to steady state initially can only be estimated. The proper value of the output voltage of the voltage-controlled oscillator must be known to produce the correct oscillator output frequency signal. Without this information, the proper charge required on the feedback capacitor when the reference signal varies can only be estimated. Likewise, the output of the pretune circuit can only approximate the proper voltage and frequency output of the voltage-controlled oscillator.
In the pretune circuit, a voltage from the digital-to-analog converter is permanently added to the voltage output of the amplifier and that sum is fed to the voltage-controlled oscillator. The value of the pretuned permanent voltage is dependent upon the estimated value of the output voltage of the voltage-controlled oscillator.
Thus, a problem that exists in the pretune circuit is that any electrical noise or distortion riding on the permanently applied pretuned voltage adds electrical noise to the input of the voltage-controlled oscillator. Therefore, if the pretuned voltage varies, then the controlled voltage tracking the variation in the reference voltage of the incoming signal also varies. However, this variation in the controlled voltage does not reflect a variation in the reference voltage. Note that the precharge circuit depends upon the relation between the charge on the capacitor and the voltage across the capacitor, as is illustrated in Equation (7). EQU V=Q/C (7)
If the charge on the capacitor could be changed instantly, the voltage across the capacitor and thus the voltage output of the amplifier could also be changed instantly, substantially reducing the settling time even further. Unlike the pretune circuit, the precharge circuit is disconnected after the feedback capacitor is charged and does not add additional electrical noise. However, this circuit is complicated. The basic disadvantage remains in that the relationship between the voltage output and the frequency output of the voltage-controlled oscillator is only approximately known.
A further modification to the phase lock loop includes the adaptive loop which changes the loop bandwidth as the loop settles. The amplifier includes two feedback paths, each path including a capacitor with a switch. The two paths are in parallel and the feedback path connected at any particular time depends upon the switch which is closed. A first feedback path provides a broad bandwidth loop having a fast settling time while the second feedback path provides a narrow bandwidth loop having a slower settling time.
After a variation in the reference voltage, the first switch connects the broad bandwidth feedback path across the amplifier providing a fast settling time. In order to reduce the amount of electrical noise and spurs, the first switch is opened and the second switch is closed connecting the narrow bandwidth feedback path across the loop amplifier providing a slower settling time.
The narrow bandwidth feedback path increases the spectral purity and reduces the electrical noise. At the time the second switch is operated, the second feedback capacitor is not charged. Thus, the amplifier output voltage is forced to zero and the precharge circuit puts an initial charge across the second feedback capacitor. However, as with previous circuits, the charge applied to the feedback capacitor by the precharge circuit is only an estimate as to what is required.
It is obvious from the above that those concerned with the development and use of fast settling phase lock loops have long recognized the need for improved phase lock loops which enable the loop to settle in a rapid manner while employing a final narrow loop bandwidth. The present invention fulfills all of these needs.